Chalcogenide materials are an emerging class of commercial electronic materials that exhibit switching, memory, logic, and processing functionality. The basic principles of chalcogenide materials were developed by S. R. Ovshinsky in the 1960's and much effort by him and others around the world since then have led to advancements of the underlying science and an expansion of the field of application of chalcogenide materials.
Early work in chalcogenide devices demonstrated electrical switching behavior in which switching from a resistive state to a conductive state was induced upon application of a voltage at or above the threshold voltage of the active chalcogenide material. This effect is the basis of the Ovonic Threshold Switch (OTS) and remains an important practical feature of chalcogenide materials. The OTS provides highly reproducible switching at ultrafast switching speeds for over 1013 cycles. Basic principles and operational features of the OTS are presented, for example, in U.S. Pat. Nos. 3,271,591; 5,543,737; 5,694,146; and 5,757,446; the disclosures of which are hereby incorporated by reference, as well as in several journal articles including “Reversible Electrical Switching Phenomena in Disordered Structures”, Physical Review Letters, vol. 21, p. 1450-1453 (1969) by S. R. Ovshinsky; “Amorphous Semiconductors for Switching, Memory, and Imaging Applications”, IEEE Transactions on Electron Devices, vol. ED-20, p. 91-105 (1973) by S. R. Ovshinsky and H. Fritzsche; the disclosures of which are hereby incorporated by reference.
Another important application of chalcogenide materials is in electrical and optical memory devices. One type of chalcogenide memory device utilizes the wide range of resistance values available for the active chalcogenide material as the basis of memory operation. Each resistance value corresponds to a distinct structural state of the chalcogenide material and one or more of the states can be selected and used to define operational memory states. Chalcogenide materials exhibit a crystalline state or phase as well as an amorphous state or phase. Different structural states of a chalcogenide material differ with respect to the relative proportions of crystalline and amorphous phase in a given volume or region of chalcogenide material. The range of resistance values is bounded by a set state and a reset state of the chalcogenide material. The set state is a low resistance structural state whose electrical properties are primarily controlled by the crystalline portion of the chalcogenide material and the reset state is a high resistance structural state whose electrical properties are primarily controlled by the amorphous portion of the chalcogenide material.
Each memory state of a chalcogenide memory material corresponds to a distinct resistance value and each memory resistance value signifies unique informational content. Operationally, the chalcogenide material can be programmed into a particular memory state by providing energy, most commonly an electric current pulse of appropriate amplitude and duration, to transform the chalcogenide material into the structural state having the resistance value associated with the particular informational content to be stored. By controlling the amount of energy provided to a chalcogenide material, it is possible to control the relative proportions of crystalline and amorphous phase regions within a volume of the material and to thereby control the structural (and memory) state of the chalcogenide material.
Each memory state can be programmed by providing the current pulse characteristic of the state and each state can be identified or read in a non-destructive fashion by measuring the resistance. Programming among the different states is fully reversible and the memory devices can be written and read over a repeated number of cycles to provide robust and reliable operation. The variable resistance memory functionality of chalcogenide materials is currently being exploited in the OUM (Ovonic Universal (or Unified) Memory) devices that are expected to appear on the market soon. Basic principles and operation of OUM type devices are presented, for example, in U.S. Pat. Nos. 6,859,390; 6,774,387; 6,687,153; and 6,314,014; the disclosures of which are incorporated by reference herein as well as in several journal articles including “Low Field Amorphous State Resistance and Threshold Voltage Drift in Chalcogenide Materials”, published in IEEE Transactions on Electron Devices, vol. 51, p. 714-719 (2004) by Pirovana et al.; and “Morphing Memory” published in IEEE Spectrum, vol. 167, p. 363-364 (2005) by Weiss.
The behavior (including switching, memory, and accumulation) and chemical compositions of chalcogenide materials included within the scope of this invention have been described, for example, in U.S. Pat. Nos. 6,671,710; 6,714,954; 6,087,674; 5,166,758; 5,296,716; 5,536,947; 5,596,522; 5,825,046; 5,687,112; 5,912,839; and 3,530,441, the disclosures of which are hereby incorporated by reference. These references also describe proposed mechanisms that govern the behavior of the chalcogenide materials. The references also describe the structural transformations from the crystalline state to the amorphous state (and vice versa) via a series of partially crystalline states in which the relative proportions of crystalline and amorphous regions vary underlying the operation of electrical and optical chalcogenide materials. Similar structural transformations have been reported more recently for the pnictide family of materials.
Current development of the chalcogenide materials and devices is also oriented toward the fabrication of arrays of devices. Chalcogenide materials offer the promise of high density memory, logic and neural arrays that can operate according to traditional binary data storage or according to a multilevel scheme. Chalcogenide arrays further offer the prospect of integrating, on a single chip, both memory and processing capabilities, thereby enabling high speed operation.
In order to expand the commercial opportunities for chalcogenide or pnictide phase-change memories, it is necessary to identify phase-change materials, device structures, and methods of programming that lead to optimized performance. Among the desirable operational characteristics are a high contrast between the resistances of the reset state and set state, low reset current, scalability of performance with decreasing device size, fast crystallization, reproducible performance over multiple cycles of operation, avoidance or inhibition of atomic migration, compositional stability, good adhesion between the active phase-change material and the electric contacts and surrounding layers of the device, stable long term storage of data, and consistent performance over a wide range of ambient conditions (including temperature and working environment).